In an active-matrix liquid crystal display apparatus, various control signals, causing a liquid crystal panel to be driven, are generated. These control signals are signals for controlling circuits such as a scanning signal line driving circuit, a data signal line driving circuit, and a power supply circuit. The following describes a general arrangement of such a liquid crystal display apparatus.
FIG. 8 is a block diagram illustrating a liquid crystal display apparatus 31. The liquid crystal display apparatus 31 is arranged so as to include a display panel 32, a control circuit 37, a timing signal generating circuit 38, and a power supply circuit 39. The display panel 32 includes a display section 34 having pixels PIX aligned in a matrix manner, a scanning signal line driving circuit 35, and a data signal line driving circuit 36. The scanning signal line driving circuit 35 and the data signal line driving circuit 36 drive each of the pixels PIX. The scanning signal line driving circuit 35 includes a shift register 35a. The data signal line driving circuit 36 includes a shift register 36a and a sampling circuit 36b. 
The display section 34, the scanning signal line driving circuit 35, and the data signal line driving circuit 36 are monolithically formed on a single substrate. This causes labor to be saved during manufacture and wiring capacity to be reduced. In addition, the display section 34, the scanning signal line driving circuit 35, and the data signal line driving circuit 36 are realized by an element such as a polycrystalline silicon thin film transistor formed on a glass substrate. This makes it possible to provide more pixels PIX so as to expand a display area. The polycrystalline silicon thin film transistor is manufactured at a processing temperature of 600° C. or lower so that the glass substrate has no warpage, caused by a process that is carried out at the strain point or higher, even when a general glass substrate having a strain point of 600° C. or lower is used.
The scanning signal line driving circuit 35 and the data signal line driving circuit 36 sequentially write, through the scanning signal lines GL1 through GLm and the data signal lines SD1 through SDk, video signals DAT supplied from the control circuit 37, into areas of the pixels PIX which are formed by causing the display section 34 to be comparted by scanning signal lines GL1 through GLm and data signal lines SD1 through SDk which are intersected with each other. This causes the display section 34 to carry out an image display. Each of the pixels PIX is arranged as illustrated in FIG. 9, for example. In FIG. 9, a pixel PIX, scanning signal line GL and data signal line SD are given an integer “i” that is not more than the integer “k” and an integer “j” that is not more than the integer “m.” These integers “i” and “j” represent an address.
Each of the pixels PIX includes a field effect transistor (switching element) SW and a pixel capacitance Cp. The field effect transistor SW has (i) a gate connected to a scanning signal line GL, (ii) a source connected to a data signal line SD, and (iii) a drain connected to one electrode of the pixel capacitance Cp. The other electrode of the pixel capacitance Cp is connected to a common electrode line that is shared by all of the pixels PIX. The pixel capacitance Cp is composed of a liquid crystal capacitance CL, and an auxiliary capacitance Cs which is additionally provided if necessary.
When the scanning signal line GL is selected, the field effect transistor SW is turned on. This causes a voltage applied to the data signal line SD to be applied to the pixel capacitance Cp. While the field effect transistor SW is turned off after a period, during which the scanning signal line GL is selected, elapses, the pixel capacitance Cp holds a voltage applied when the field effect transistor SW is turned off. Transmittance or reflectivity of liquid crystal varies depending on a voltage applied to the liquid crystal capacitance CL. Accordingly, a display state of a pixel PIX can be changed in accordance with a video signal DAT, by selecting a scanning signal line GL and applying to a data signal line SD a voltage which varies in accordance with a video signal DAT.
A video signal DAT to be ultimately supplied to each of the pixels PIX is transmitted from the control circuit 37 to the data signal line driving circuit 36 in a time-shared manner. The data signal line driving circuit 36 extracts, from the video signal DAT, video data to be supplied to each of the pixels PIX, at a timing obtained on the basis of a source clock signal SCK, its inverted signal SCKB, a source start pulse SSP, and its inverted signal SSPB. These signals, supplied from the timing signal generating circuit 38 to the data signal line driving circuit 36, are timing signals. The source clock signal SCK and its inverted signal SCKB each have (i) a predetermined cycle and (ii) a duty ratio of 50% (may have respective duty ratios of not more than 50%). Specifically, the shift resister 36a sequentially shifts source start pulses SSP and SSPB in sync with timing at which supplied source clock signals SCK and SCKB become active. This causes output signals S1 through Sk to be generated. The output signals S1 through Sk have respective timings which are different from each other by a half cycle of the source clock signals SCK and SCKB. The sampling circuit 36b samples the video signal DAT at the timing indicated by the output signals S1 through Sk, and outputs the video data thus sampled to the data signal lines SD1 through SDk, respectively. A power supply voltage supplied from the power supply circuit 39 to the data signal line driving circuit 36 is used as analog voltages to be supplied to the data signal lines SD1 through SDk.
Similarly, in the scanning signal line driving circuit 35, the shift resister 35a sequentially shifts gate start pulses GSP and GSPB in sync with gate clock signals GCK and GCKB, which are supplied from the timing signal generating circuit 38. Accordingly, scanning signals having respective timings which are different from each other by a predetermined period are outputted to the scanning signal lines GL1 through GLm.
The timing signal generating circuit 38 generates timing signals such as the source clock signals SCK and SCKB, the source start pulses SSP and SSPB, the gate clock signals GCK and GCKB, and the gate start pulses GSP and GSPB. Among them, the gate start pulses GSP and GSPB, serving as a kind of display driving control signal, are generated so as to be in sync with a signal HSYNC, which is a horizontal blanking interval synchronization signal supplied from the control circuit 37. In addition, the timing signal generating circuit 38 generates, in sync with a signal VSYNC, power supply control signals, such as a discharge signal DIS, a charge signal CHA, an enable signal EN, for controlling the power supply circuit 39, and then the power supply control signals are supplied to the power supply circuit 39. The signal VSYNC is a vertical blanking interval synchronization signal supplied from the control circuit 37. The discharge signal DIS is a control signal for causing the power supply circuit 39 to discharge its inside at a startup of the power supply circuit 39. The charge signal CHA is a control signal for charging the power supply circuit 39 so that the power supply circuit 39 can prepare for a startup after the power supply circuit 39 is caused to be discharged in response to the discharge signal DIS. The enable signal EN is a control signal for enabling a clock signal that causes the power supply circuit 39 to operate after the power supply circuit 39 is charged in response to the charge signal CHA. The timing signal generating circuit 38 may generate the source start pulses SSP and SSPB in sync with a dot clock signal.
The control circuit 37 generates signals such as a video signal DAT, signals VSYNC and HSYNC, based on a control signal and a video signal that are externally supplied. The liquid crystal display apparatus 31 supplies, via its power supply section, power to the control circuit 37 and the power supply circuit 39. The power supply circuit 39 also supplies power to the scanning signal line driving circuit 35, a common voltage of the display section 34, and the like, in addition to the power to be supplied to the data signal lines SD1 through SDk, as described above.
The above has schematically described the arrangement of the liquid crystal display apparatus 31. The following describes an arrangement of the timing signal generating circuit 38 in detail.
As illustrated in FIG. 10, a conventional timing signal generating circuit 38 separately includes (i) a VSYNC synchronous counter 41 for generating a signal being in sync with a signal VSYNC and (ii) an HSYNC synchronous counter 42 for generating a signal being in sync with a signal HSYNC. The pulse signals VSYNC and HSYNC are input pulse signals to be supplied to the respective synchronous counters. The input pulse signals VSYNC and HSYNC are counted by the synchronous counters, and are also synchronization signals to be simultaneously supplied to clock terminals of flip-flops of the synchronous counters, respectively. Based on a counted result made by the VSYNC synchronous counter 41, a VSYNC synchronization control signal generating circuit 43 generates various control signals being in sync with a signal VSYNC. Likewise, based on a counted result made by the HSYNC synchronous counter 42, an HSYNC synchronization control signal generating circuit 44 generates various control signals being in sync with a signal HSYNC.
FIG. 11 is a timing diagram illustrating a relation between the signals VSYNC and HSYNC and the control signals generated based on the results of counting the signals VSYNC and HSYNC.
FIG. 11 shows early signals in a power-up period and in a subsequent display period. The power-up period ends at the time when the VSYNC synchronous counter 41 counts 8 pulses of the signal VSYNC. Then, a display period begins. During a power-up period, generated are power supply control signals being in sync with the signal VSYNC. For example, when a rising edge of the second pulse of the signal VSYNC is counted, a discharge signal DIS is generated. When a rising edge of the third pulse of the signal VSYNC is counted, a charge signal CHA is generated. When a rising edge of the fifth pulse of the signal VSYNC is counted, an enable signal EN is generated. In FIG. 11, a discharge signal DIS and a charge signal CHA have the same pulse width corresponding to two cycles of the signal VSYNC. An enable signal EN remains active from its rising edge to the end of a display period. During a display period, generated is a display driving control signal being in sync with a signal HSYNC. For example, a gate start pulse GSP is generated when the HSYNC synchronous counter 42 counts the (N−1)th falling edge (N≦7) of a pulse signal HSYNC after a falling edge of a pulse signal VSYNC. A gate start pulse GSP has a pulse width corresponding to one cycle of a signal HSYNC, and falls in sync with the N-th falling edge of the pulse signal HSYNC.
[Patent Document 1]
    Japanese Unexamined Patent Publication No. 90873/1991 (Tokukaihei 3-90873 (Date of publication: Apr. 16, 1991))